A liquid crystal display comprises a liquid crystal panel and a backlight portion equipped with a light source provided on the back surface thereof. Each pixel in the liquid crystal panel transmits light emitted from the backlight portion as the liquid crystals are driven according to a video signal so that an image is displayed on the liquid crystal panel.
Generally, a fluorescent tube (fluorescent lamp) is used often as the light source in the backlight portion. In the fluorescent tube, a hollow glass tube is filled with a discharge gas, mercury, and the like. A discharge occurs as a high voltage is applied to the electrode tubes disposed at the both ends of the fluorescent tube. A vapor of mercury inside the tube is excited by receiving high energy generated by this discharge, and a UV ray is emitted when the vapor of mercury returns to a low energy state again. Also, a fluorescent material is applied on the interior of the tube, and light is emitted when the UV ray is changed to a visible ray.
As has been described, it is necessary to apply a high voltage to cause the fluorescent tube to emit light. Generally, DC power at a low voltage is converted to AC power at a high voltage and a high frequency (about 30 kHz to 100 kHz) using a power supply circuit known as an inverter and applied to the fluorescent tube.
The voltage dimming method and the PWM (Pulse Width Modulation) dimming method are used as a method in the related art for dimming the fluorescent tube using the inverter. The voltage dimming method is a dimming method by which a voltage applied to the fluorescent tube is varied via the inverter. However, a discharge becomes unstable when an applied voltage to the fluorescent tube is lowered exceedingly. Hence, a stable dimming ratio in the voltage dimming method is 2 to 3:1, which makes it impossible to secure a broad dimming range.
Meanwhile, the PWM dimming method is a method of performing dimming by blinking the light source periodically while varying a time ratio of the light-ON period and the light-OFF period. Hence, by choosing the blinking cycles appropriately, it is possible to achieve a dimming ratio of 100:1. The PWM dimming method is therefore adopted in many liquid crystal displays to control the backlight.
When the PWM dimming method is used, however, a flicker (flickering) occurs because the display driving cycle of the liquid crystal panel does not coincide with the blinking cycle of the light source in the backlight portion, and the luminance becomes unstable. This makes a flicker noticeable in some images displayed on the liquid crystal panel. Regarding a flicker, human eyes are insensitive to a flicker when a flickering frequency is high to some extent. In a case where the PWM dimming method is applied to a liquid crystal display that is equipped with the backlight and displays a video signal on the screen according to a horizontal synchronization signal and a vertical synchronization signal, in order to prevent a flicker, it is necessary to set the PWM dimming frequency fPWM sufficiently larger than a vertical synchronization frequency fV of the liquid crystal panel to establish fPWM >>fV. When configured in this manner, it is possible to prevent the occurrence of a flicker even when the PWM dimming pulse and the synchronization signal of the liquid crystal panel are asynchronous.
For example, when the vertical synchronization frequency fV is 60 Hz, it is ideal to set the PWM dimming frequency fPWM to about 600 Hz, which is a frequency ten times the vertical synchronization frequency fv. However, when the PWM dimming frequency becomes so high, light ON efficiency of the inverter is deteriorated and audible sounds (whining sounds) from the inverter transformer are increased as adverse effects. The PWM dimming frequency fPWM therefore cannot be set much higher. For this reason, generally, the PWM dimming frequency fPWM is often set to be a frequency of 400 Hz or lower.
As a liquid crystal display in the related art that improves the occurrence of a flicker and instability of luminance even at the low PWM dimming frequency as specified above, a liquid crystal display disclosed, for example, in Patent Document 1 has been used. FIG. 29 is a block diagram showing the configuration of the liquid crystal display in the related art.
The liquid crystal display in the related art shown in FIG. 29 comprises a liquid crystal module 100, a video processing portion 200, a PWM dimming driving circuit portion 300, and a backlight portion 400. The liquid crystal module 100 comprises a panel control circuit 111, a source driver 112, a gate driver 113, and a liquid crystal panel 114. The video processing portion 200 comprises a video signal processing circuit 221 and a system control circuit 222.
The video signal processing circuit 221 generates video signals VR, VG, and VB for respective three primary colors, a vertical synchronization signal Vsyn, a horizontal synchronization signal Hsyn, and a pixel clock CLK from an input video signal. The panel control circuit 111 outputs the video signals VR, VG, and VB and the clock pulse CLK to the source driver 112, and outputs the vertical synchronization signal Vsyn and the horizontal synchronization signal Hsyn to the gate driver 113. The source driver 112 and the gate driver 113 apply source voltages corresponding to the video signals VR, VG, and VB to the signal electrodes while scanning the gate electrodes of the liquid crystal panel 114 according to the respective synchronization signals Vsyn and Hsyn for an image to be displayed on the liquid crystal panel 114.
The PWM dimming driving circuit portion 300 comprises a divide two vertical periods by five circuit 331, a ½ frequency-dividing circuit 332, a pulse count circuit 333, and a PWM generation circuit 334. The ½ frequency-dividing circuit 332 outputs a frequency-divided signal 2Tv by ½ frequency-dividing the vertical synchronization signal Vsyn for the liquid crystal panel. The divide two vertical periods by five circuit 331 outputs a dividing signal 2/5Tv that divides two vertical periods by five according to the frequency-divided signal 2Tv. The pulse count circuit 333 is reset by the dividing signal 2/5Tv, and after it is reset, it generates a reset pulse Pr by counting a specific number of clock pulses pre-set by duty data of a digital control signal for dimming received from the system control circuit 222. The PWM generation circuit 334 generates a PWM dimming pulse Vpwm that determines a light-ON period of the backlight portion 400 according to the dividing signal 2/5Tv and the reset pulse Pr.
FIGS. 30A through 30E are timing charts of the respective signals inputted into and outputted from the PWM dimming driving circuit portion 300 shown in FIG. 29. It is understood from FIGS. 30A through 30E that five cycles' worth of PWM dimming pulses Vpwm are outputted within two vertical periods. An effect achieved by the driving using such a PWM dimming method will be described hereinafter.
FIGS. 31A and 31B are views in which PWM dimming pulses of a first screen and a second screen within two vertical periods are aligned for ease of understanding of timing with respect to the vertical synchronization signal. FIG. 31A shows a case where six cycles' worth of PWM dimming pulses are outputted within two vertical periods, and FIG. 31B shows a case where five cycles' worth of PWM dimming pulses are outputted within two vertical periods. In FIGS. 31A and 31B, a time ratio of a light-ON period and a light-OFF period of the PWM dimming is set to 1:1 (generally referred to as the light-ON duty of 50%) for ease of description.
In a case where six cycles' worth of PWM dimming pulses are outputted within two vertical periods, as is shown in FIG. 31A, given that the timing from the vertical synchronization signal is the same, then, the timings of the light-ON period and the light-OFF period become exactly the same in the first screen and the second screen within the two vertical periods when driven using the PWM dimming frequency obtained by multiplying (by a factor of 3 herein) the vertical synchronization frequency, and the PWM dimming pulses become the same outputs.
Meanwhile, in a case where five cycles' worth of PWM dimming pulses are outputted within two vertical periods, as is shown in FIG. 31B, the timings of the light-ON period and the light-OFF period become totally opposite in the first screen (first frame) and the second screen (second frame) within the two vertical periods. This results in an effect close to that achieved when blinking is performed twice as much during a certain period by the PWM dimming method. In other words, when attention is focused on one vertical period alone, the PWM dimming cycles are 2.5 cycles. However, when the two vertical periods are averaged, the PWM dimming frequency behaves as if it had doubled apparently. The same effect can be achieved when the PWM dimming pulses outputted within the two vertical periods are odd-number cycles' worth. For example, in a case where blinking is performed by setting the PWM dimming frequency to 330 Hz when the vertical synchronization frequency is 60 Hz, 5.5 cycles' worth of PWM dimming pulses are outputted within one vertical period. The flicker reducing effect is the same as a frequency of about 660 Hz, which is a frequency twice the PWM dimming frequency.
Capabilities required for the liquid crystal display as a display device include the motion picture display capability, and the liquid crystal display is inferior to the CRT in terms of the motion picture display capability. This is because the liquid crystal display is a hold-type display device, and the underlying principle is described in Non-Patent Document 1, which will be described briefly hereinafter.
FIGS. 32A and 32B are schematic views used to describe the motion picture display capability of a CRT. When a motion picture is displayed on the CRT that has been used extensively, as is shown in FIG. 32A, a level at which an image is displayed varies in every vertical period (16.6 ms), and the image is displayed only during the initial period (1 ms or less) in each vertical period. A display device that displays a motion picture in this manner is referred to as an impulse type display device. In a case where a motion picture is displayed on such a CRT (when a display is moved at a constant speed), the image is displayed as is shown in FIG. 32B. When a human sees this display, the line of sight follows a display of the pixels in the direction indicated by an arrow. He is therefore able to perceive a clear motion picture display with no after image.
FIGS. 33A and 33B are schematic views used to describe the motion picture display capability of a liquid crystal display. In FIGS. 33A and 33B, for ease of description, pixels in the time direction are indicated by three points (black circles in the drawing) for each vertical period. Because the liquid crystal display is a hold-type display device, as is shown in FIG. 33A, a display on the liquid crystal panel remains the same over one vertical period (it actually varies by an amount comparable to a response time), and the luminance varies in each vertical period. In a case where a motion picture is displayed on the liquid crystal display, pixels are displayed as are shown in FIG. 33B. When a human sees this display, although the line of sight follows the direction indicated by an arrow as with the case of the CRT, the human eyes perceive the display on average because the display remains the same over one vertical period, and the edge of the motion picture being displayed becomes blur (referred to as the edge blur or motion picture blur), which deteriorates the motion picture display capability.
There is a display method disclosed, for example, in Patent Document 2 as a method of improving the edge blur described above. FIG. 34 is a view used to describe the display method of improving the edge blur. According to the display method shown in FIG. 34, attention is focused on a given pixel, and a light-OFF period during which the light source in the backlight portion is lit OFF for a certain period is provided within one vertical period in sync with the vertical synchronization signal. By driving the light source in this manner, as with the impulse type display device, such as the CRT, the liquid crystal display displays an image for a certain period within one vertical period. The edge blur during the display of a motion picture can be therefore improved. In this specification, this dimming method is referred to as the black insertion dimming by the backlight.
The effect of the black insertion dimming by the backlight will now be described more concretely. FIGS. 35A and 35B are views showing an example of a display pattern to evaluate the effect of the black insertion dimming by the backlight. FIG. 36 is a schematic view used to describe a perception state in a case where the black insertion dimming by the backlight is not performed. FIG. 37 is a schematic view used to describe a perception state in a case where the black insertion dimming by the backlight is performed. In FIG. 36 and FIG. 37, black circles represent light-OFF pixels and white circles represent light-ON pixels.
As is shown in FIG. 35A, in a case where a scroll display to move a white pattern WP on a black background BP at a constant speed Xf (a moving distance in one vertical period) is performed, as is shown in FIG. 35B, the both edge portions of the white pattern WP in the moving direction become blur, thereby giving rise to the edge blur.
In a case where the black insertion dimming by the backlight is not performed, as is shown in FIG. 36, the light-ON pixels and the light-OFF pixels are switched collectively per vertical period. Accordingly, one light-ON pixel and three light-OFF pixels are successively displayed in a moving direction V1 of the line of sight, two light-ON pixels and two light-OFF pixels are successively displayed in a moving direction V2 of the line of sight, and three light-ON pixels and one light-OFF pixel are successively displayed in a moving direction V3 of the line of sight. Consequently, the moving direction V1 of the line of sight is perceived at the lowest brightness, the moving direction V3 of the line of sight is perceived at the highest brightness, and the moving direction V2 of the line of sight is perceived at the intermediate brightness between those in the other two directions. Hence, as is shown in FIG. 35B, the both edge portions of the white pattern WP in the moving direction are perceived as being blurred.
On the contrary, in a case where the black insertion dimming by the backlight is performed, as is shown in FIG. 37, all the pixels are lit OFF during the black insertion period within one vertical period, and the light-ON pixels and the light-OFF pixels are switched collectively per vertical period during the rest period within the vertical period. Accordingly, one light-ON pixel and three light-OFF pixels are successively displayed in the moving direction V1 of the line of sight, two light-ON pixels and two light-OFF pixels are successively displayed in the moving directions V2 and V3 of the line of sight. Consequently, the moving direction V1 of the line of sight is perceived at the lowest brightness and the moving directions V2 and V3 of the line of sight are perceived at the same brightness. Hence, the degree of blur at the both edge portions of the white pattern WP in the moving direction shown in FIG. 35B is lowered, and the motion picture visibility is improved.
However, because an image is displayed on the liquid crystal panel by successively performing scans from top to bottom, when the backlight portion is lit ON and lit OFF for the entire screen within one vertical period as described above, the edge blur becomes inhomogeneous during the display of a motion picture through the action of a response speed of the liquid crystals. As a liquid crystal display that improves such non-uniformity, there is a liquid crystal display disclosed, for example, in Patent Document 3.
FIG. 38 is a block diagram showing the configuration of a major portion of the liquid crystal display in the related art that improves the non-uniformity of the edge blur. As is shown in FIG. 38, a backlight 401 is divided by M in the horizontal direction (divided by four in the case of FIG. 38) to form light-emission regions 444a through 444d, and fluorescent lamps 443a through 443d are disposed respectively in these regions. The fluorescent lamps 443a through 443d are connected to inverters 442a through 442d, respectively, and the inverters 442a through 442d are connected to a PWM dimming driving circuit portion 301. The PWM dimming driving circuit portion 301 receives a vertical synchronization signal Vsyn for a liquid crystal panel display, and outputs a PWM dimming pulse (the PWM frequency is equal to the vertical synchronization frequency) that controls the dimming by the respective inverters 442a through 442d in sync with the vertical synchronization signals Vsyn. The inverters 442a through 442d respectively drive the fluorescent lamps 443a through 443d independently.
FIGS. 39A through 39E are timing charts of the respective signals in the liquid crystal display in the related art shown in FIG. 38. As is shown in FIGS. 39A through 39E, for example, a PWM dimming pulse VBL1 of the light-emission region 444a shifts to dimming-OFF immediately before a display of the liquid crystal directly above starts and holds a certain light-OFF period. A PWM dimming pulse of the light-emission region 444b is set in such a manner that dimming-ON and dimming-OFF timings are delayed with respect to the PWM dimming pulse VBL1 by a ¼ phase of the vertical synchronization period. Thereafter, dimming-ON and dimming-OFF timings for the light-emission regions 444c and 444d are set so as to be delayed by a ¼ of the vertical synchronization period with respect to one to another. By successively lighting ON the divided fluorescent lamps 443a through 443d directly below in sync with the vertical synchronization signal through the PWM dimming to correspond to a scanning display on the liquid crystal panel, it is possible to improve the non-uniformity while improving the edge blur.
As has been described, it is possible to improve the non-uniformity while improving the edge blur with the use of the black insertion dimming by the backlight. However, because the light-OFF period can be set only once within one vertical period in the black insertion dimming by the backlight, it is impossible to blink the light source periodically at a frequency as high as the frequency of the PWM dimming, which makes it difficult to perform the dimming in a stable manner at a low current.
It may be possible to use the light-OFF period of the PWM dimming as the light-OFF period of the black insertion dimming by the backlight. It is, however, necessary to lower the PWM frequency when a light-OFF period of a certain period or longer is inserted while maintaining a duty ratio of the PWM dimming pulse at a constant level. In this case, the screen becomes darker, which makes the dimming in a bright region difficult.
The result is the same as above in a case where a light-OFF period of a certain period or longer is inserted without varying the PWM frequency as will be described below. FIGS. 40A through 40D are timing charts showing driving waveforms in a case where a light-OFF period as long as the period of the black insertion dimming by the backlight is inserted without varying the PWM frequency. As is shown in FIGS. 40A through 40D, in a case where a light-OFF period by the PWM driving (PWM dimming) in the related art shown in FIG. 40C is changed to be as long as the light-OFF period of the black insertion period by the black insertion driving (black insertion dimming by the backlight) in the related art shown in FIG. 40B, the light-OFF period of the PWM dimming becomes as is shown in FIG. 40D. When a light-OFF period of a certain period or longer is inserted without varying the PWM frequency in this manner, it becomes necessary to extend the low period of the PWM dimming pulse (substantially equivalent to the black insertion period). Hence, in this case, too, the screen becomes darker, which makes the dimming in a bright region difficult.
Further, it may be possible to combine the black insertion dimming by the backlight and the PWM dimming. However, when the black insertion dimming by the backlight and the PWM dimming are merely combined, problems as follows are posed. FIGS. 41A through 41D are timing charts used to describe unwanted pulses generated when the black insertion dimming by the backlight and the PWM dimming are combined.
Assume that the black insertion dimming by the backlight is performed to improve the edge blur and a PWM dimming pulse Vpwm in sync with the vertical synchronization signal Vsyn of the liquid crystal panel is superimposed to adjust the luminance. Herein, as has been described above, when the PWM dimming is performed in an interleave relation with respect to the vertical synchronization signal Vsyn to suppress a flicker in a display on the liquid crystal panel, as is shown in FIGS. 41A through 41D, a PWM dimming pulse VBL (the PWM dimming frequency is equal to the vertical synchronization frequency, for example, 60 Hz) of the black insertion dimming by the backlight interferes with a PWM dimming pulse Vpwm by the interleave. It is therefore anticipated that a whisker-shaped pulse BP having an extremely small duty is generated near the timing of the falling edge of the vertical synchronization signal Vsyn once within two vertical periods under the condition that the duty (a time ratio of the light-ON period with respect to the dimming cycle) of the PWM dimming pulse exceeds 50%.
A case where the backlight is successively lit ON is the same as the black insertion dimming when attention is focused on every light-emission region. Hence, it is anticipated that a whisker-shaped pulse is generated as well. Because such a whisker-shaped pulse has an extremely narrow duty (a time ratio of 1% or less), a light-ON action corresponding to the duty cannot be performed; moreover, a malfunction may possibly be induced in some inverters.
Patent Document 1: JP-A-7-325286
Patent Document 2: JP-T-8-500915
Patent Document 3: JP-A-11-202285
Non-Patent Document 1: Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, EID99-10, pp. 55-60 (1999-06)